The main function of an integrated circuit (IC) package is to protect, power, and cool an IC device within the package and provide thermal, electrical, and mechanical connections to properly interface with a larger system such as a Printed Circuit Board (PCB).
FIG. 1 shows an example of such an IC package. The area on the bottom side of FIG. 1 is a PCB 21. On top of the PCB 21, an IC package is provided which comprises a plurality of connection points 32, one or more ground structures 28 which connect the package to ground, a power supply 30 which provides power to the package, a plurality of transmission lines 34 and one or more vias 36 inside of the package. A die 24 connects to the IC package via a plurality of bond wires 26. The IC package provides a signal path 22 (the dotted line depicted in FIG. 1) from the die 24 to a receiver circuit mounted on another area of the PCB 21.
The signal path 22 comprises: 1) a bonding structure from the die 24 to the bond wires 26 that act as an interface between the die 24 and the package, 2) transmission lines 34 which are inside of the package and 3) vias 36 in the right-bottom part of the FIG. 1 that provide one or more vertical connections to one or more connection points 32.
Normally the process of manufacturing an IC package comprises four main procedures:                1) A wafer is separated into IC chips (dies) by a diamond saw; normally this step is called a die separation step.        2) The separated die is bonded into the center of a lead frame or package; normally this step is called a die attachment step.        3) The pads on the IC chip and adjoining terminals on the lead frame are connected, one-by-one, with gold, copper or aluminum wires; normally this step is called a wire bonding step.        4) The chip is sealed with a macro-molecule plastic, like epoxy resin, thus finishing the plastic package container. The lead frame is cut, and leads are bent thus forming the package. This procedure is commonly called “Glob Top” assembly or encapsulation.        
During the die attachment step, two different technologies may be used: a) wire bond attachment, and b) flip-chip attachment. FIG. 2A describes the wire bond attachment and FIG. 2B describes the flip-chip attachment in more detail.
The wire bond method described by FIG. 2A is the most widely used method. The left side of FIG. 2A is a side view of the wire bond method, the right side of FIG. 2A is a top view of the wire bond method. The wire bond 26 is simply a very small wire with a diameter of about 0.0254 mm. The bond wire lengths vary from approximately 1.27 mm to 12.7 mm. The die 24 is mounted onto the package with a plurality of pads 46 on top. The bond wire 26 connects both the die 24 and a further pad 40 which is on the package. The advantage of the wire bond method is that it is inexpensive, mechanically simple, and allows for some changes in the bonding pad location and package routing. Furthermore, since the back of the die 24 is attached directly to the package substrate, it allows maximum surface area contact between the die and the package, which maximizes heat transfer out of the die 24.
The flip-chip attachment method described in FIG. 2B is another widely used method. The left side of FIG. 2B is a side view of the flip-chip attachment method and the right side of FIG. 2B is a bottom view of the flip-chip attachment method. The die 24 is mounted onto the package with a plurality of package bond pads 46 on the bottom. A plurality of small solder balls 42 are located on pads of the die 24 in order to make a connection between the die 24 and the substrate. The die 24 is then placed upside down on the package and the solder is reflowed to make an electrical connection to the package bond pads 46. Flip-chip technology is also said to be self-aligning because when the solder is re-flowed, the surface tension of solder balls will pull the die 24 into alignment with the bond pads 46 on the package. The main advantage of flip-chip attachment is that the inductance of a flip-chip connection is much lower than that of a wire bond.
During the assembly procedure, two assembly technologies are mainly used: 1) Pin-through-hole (PTH) packaging, and 2) surface mount technology (SMT) packaging. If the packages have pins that can be inserted into holes in the PCB, the technology is called through-hole packaging. If the packages are not inserted into the PCB, but are mounted on the surface of the PCB, the technique is called SMT. The advantage of the SMT, as compared to PTH, is that both sides of the PCB can be used, and therefore, higher packing density can be achieved on the PCB.
Normally, an IC package may comprise a plurality of 1) vias and 2) stubs:                1) A via is a small hole drilled through a PCB that is arranged to make connections between various layers of the PCB or connect components to one or more leads (57, 58) on a layer of the PCB. The most common type of via is called a through-hole via because it is made by drilling a hole through the board, filling it with solder, and making connections on appropriate layers via a pad. FIG. 3 shows the structure of a through-hole via. Normally a through-hole via comprises a barrel 50, one or more pads 52, and an antipad 56. As shown, the upper pad 52 connects to a lead 57 and antipad 56 connects to a lead 58 on a different layer.        2) A stub is a length of transmission line that is connected at one end only. The free end of the stub is either left open-circuited or short-circuited. Neglecting transmission line losses, the input impedance of the stub is purely reactive. Depending on the electrical length of the stub and on whether it is open or short circuit, the stub will perform either capacitively or inductively.        
The interconnections in PCBs and in packages are generally considered as transmission lines. The transmission line can couple energy to adjacent signal lines, which results in crosstalk. Crosstalk can cause false switching of circuits and can increase delay times. Transmission lines account for a finite propagation velocity of electrical signals. The ratio of the voltage to the current carried by a wave in a particular direction on a transmission line is the characteristic impedance of the line. Discontinuities in the characteristic impedance cause partial reflections of the waves on the line. Reflections give rise to signals traveling the wrong way on an interconnect, which can be thought of as additional noise within the system. To prevent reflections, transmission lines must be properly terminated at their ends by “matching” the load impedance to the characteristic impedance of that line.
A balun circuit is a type of electrical transformer that converts signals that are balanced about ground to signals that are unbalanced and vice versa. The balun circuit is very often also used to change impedance. It can be simply considered as a transmission line transformer. In the area of the present disclosure, where a chip could be connected to an antenna in order to transmit signals as generated on the chip, such a balun circuit is quite often used to connect the transmission line, that is connected at one end to the chip at its other end, to the antenna.
If the chip is bonded in a standard package via soldering iron (wire bond attachment), the larger the length of the associated transmission line, the worse the performance of the chip at the outside of the package will be. To counter this effect, a pre-match circuit 72 can be used between the transmission line and the balun circuit 74 which is, at its other end, connected to antenna circuit 76, as shown in FIG. 4.
In the example of FIG. 5, the pre-match circuit 72 has two input lines connected to a differential output of the chip. One of the input lines is connected to ground via a capacitor 81. The other line is connected to ground via a capacitor 82. Both capacitors 81, 82 may have a value Cp. However, their values may be different. By doing so, the input lines to the pre-match circuit 72 may have a (very) low impedance whereas the output lines of the pre-match circuit 72 may have a (very) high impedance. Such a high impedance is easier to be dealt with by designers of balun circuits. The pre-match circuit 72 is located on the die 24 or on the PCB.
The balun circuit 74 has two input lines connected to two output lines of the pre-match circuit 72. One of the input lines is connected to ground via a capacitor 83 and to an output line via an inductor 84. The other line is connected to a power supply VBAT via an inductor 85 and to another output line via a capacitor 86. Both capacitors 83, 86 may have a value Cb. However, their values may be different. Both inductors 84, 85 may have a value Lb. However, their values may be different. The power supply VBAT is connected to ground via a capacitor 87 which may have a value Cd.
Both output lines are short circuited and connected to ground via a series circuit of an inductor 110 having a value Ls and a capacitor 89 having a value Cd. Moreover, the short circuited output is connected to a single-ended output to be connected to an antenna via a capacitor 88 having a value Cc. The junction of inductor 110 and capacitor 89 is connected to power supply VBAT.
Inductors 85 and 110 are used to connect DC power supply VBAT to the balun circuit. Capacitors 87 and 89 are used for decoupling. Capacitor 88 is a coupling capacitor to the antenna. Capacitor 88 is not involved in the matching function.
In general, the output of the chip is connected to the pre-match circuit 72 by means of a transmission line. However, the pre-match circuit 72 between the chip and the balun circuit 74 which connects to the antenna may not be close enough to the chip outputs. Due to this relatively long transmission line, the (very) low impedance at the chip output transforms to an impedance with a high quality (Q) factor. This makes the pre-match circuit 72 and balun circuit 74 more sensitive for component value variations of the various inductors and capacitors in these circuits.
To solve this pre-match circuit problem, one existing solution is called “Known Good Die” (KGB). In this solution, the package is entirely removed and the chip is assembled on the Printed Circuit Board (PCB) directly close to pre-match circuit 72. The disadvantage of the KGB solution is that this assembly technique is not supported by all manufacturers since many of them prefer packaged chips. Moreover, it is more difficult to test a chip without the package.
Another known solution is called “low-temperature co-fired ceramic” (LTCC): Here, the chip is assembled on a substrate which contains the pre-match circuit 72. Subsequently, the substrate is bonded on a PCB. The pre-match circuit can exist both as a planar structure on the assembled component and as a circuit incorporated on the substrate. The disadvantage of LTCC is that the cost is very high.
Pre-match circuits integrated in a package are, for instance, known from US2008/191362, US2004/178854, and U.S. Pat. No. 6,215,377. However, such pre-match circuits may suffer from transmission of radiation at higher harmonics of signals within the pre-match circuit.